eSilicon Optimizes IP for Cost-Effective 2.5D Integration

SAN JOSE, CA--(Marketwired - Jan 8, 2015) -

Who: Lisa Minwell, senior director of marketing for the eSilicon IP Solutions Group

What: Keynote presentation: Optimizing IP for Cost-effective 2.5D Integration

Where: MEPTEC luncheon, Biltmore Hotel, Santa Clara

When:
Wednesday, January 14, 2015
Registration: 11:30am
Presentation: 12:00-1:15pm

Abstract:
Heterogeneous integration on silicon interposers provides a viable solution to the demand in the computer and consumer electronics markets for higher processing speed, lower power and increased functionalities. Lisa Minwell of eSilicon will discuss technologies and techniques for optimizing 2.5D designs for power and cost effectiveness.

About Lisa Minwell
As senior director of marketing, IP Solutions Group, eSilicon Corporation, Lisa Minwell is responsible for the company's physical IP product portfolio. Before joining eSilicon, Lisa was product marketing manager for memory products at Synopsys, Inc. and director of product marketing for Virage Logic's memory products. She held various design and managerial positions with Motorola, Inc., where her experience included memory compiler development, SRAM design engineering, CAD and IT management and research and development of DRAM and EEPROMs. Lisa holds a Bachelor of Science in Microelectronic Engineering from the Rochester Institute of Technology, Rochester, New York.

About eSilicon
eSilicon, a leading independent semiconductor design and manufacturing solutions provider, delivers custom ICs and custom IP to OEMs, independent device manufacturers (IDMs), fabless semiconductor companies (FSCs) and wafer foundries through a fast, flexible, lower-risk, automated path to volume production. eSilicon serves a wide variety of markets including communications, computer, consumer, industrial products and medical. www.esilicon.com

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