SUNNYVALE, Calif., Nov. 08, 2022 (GLOBE NEWSWIRE) -- Real Intent, Inc., today announced SafeConnect, a user-defined connectivity & glitch static sign-off tool. SafeConnect enables early RTL and netlist sign-off within IP blocks or across SoCs. Design and verification engineers can quickly define rules for various source-destination types. SafeConnect has low noise reporting and integrated debug. Its high-capacity analysis is expected to be about ten times faster than formal solutions and Tcl-based scripting.
Shift Left with Early RTL/Netlist Connectivity & Glitch Sign-Off
Real Intent SafeConnect is deployed during key stages of the IP and SoC design process.
| 1) | During RTL design -- to ensure memory, power, and debug logic connectivity, and to avoid glitches on user-specified asynchronous, multicycle, and false paths. Designers can also avoid improper connectivity that can lead to block abutment issues during layout. | ||
| 2) | Post synthesis -- to repeat the connectivity and glitch checks on the netlist. Engineers can also find and address new issues such as improper power supply rail crossing or incorrect DFT logic connectivity. |
Users Can Efficiently Define a Variety of Sign-Off Rules
Design and verification engineers can quickly and flexibly create a diverse set of rules for connectivity and glitch sign-off. Additionally, users can take advantage of Real Intent’s existing documented library of checks. Some representative rules that customers have created are:
- Extra margin adjustment memory connectivity
- Retention reset/clock correctness
- Glitch occurrence & propagation
- DFT logic MUX and debug bus checks
- Abutment & partial abutment verification
SafeConnect also allows more granular sub-checks to further reduce noise in the violation reports. Examples of sub-checks are cross connect, source miss, extra connection, and bit flip.
The specification effort is minimal due to efficient, flexible commands, compared to the tedious and error-prone CSV or complex Tcl coding required by other approaches. The tool also accepts UPF as direct input to further ease the specification effort.
Individual designers precisely control which rules and sub-checks to run and report.
SafeConnect Outperforms Scripts & Formal Approaches
Real Intent SafeConnect’s unique high capacity makes it suitable for both block level and SoC-level sign-off. Black boxing is available, but not required for large designs – unlike other solutions. Additionally:
- SafeConnect’s block-level analysis typically takes only minutes to run compared to hours for formal solutions and Tcl-based scripting for comparable blocks.
- It can be run on any design type, including designs with complex control logic and clock gating.
- SafeConnect provides low noise reports via efficient pattern matching and user-specified configurations such as destination exclusions.
- Real Intent’s familiar iDebug environment is integrated with SafeConnect, while incorporating additional functionality to enable highly focused connectivity and glitch violation debugging.
Further, only minimal ongoing maintenance and support is needed for SafeConnect, compared with the extensive effort required for Tcl-based scripting.
For more information on SafeConnect, please visit https://www.realintent.com/connectivity-glitch-sign-off-safeconnect/.
About Real Intent
Real Intent provides intent-driven static sign-off EDA software tools to accelerate early functional verification and advanced sign-off of digital designs. Its static sign-off product capabilities include multi-mode clock domain crossing; multi-scenario reset domain crossing; multi-test mode DFT; multi-policy RTL linting, connectivity & glitch, design initialization, and formal linting. Real Intent customers include more than 50 major semiconductor and systems companies. Real Intent is headquartered at 932 Hamlin Court, Sunnyvale, CA. For more information visit us at www.realintent.com.
