SC19: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Five-Meter Samtec Cable Assembly
November 14, 2019 08:00 ET
|
eSilicon Corporation
SAN JOSE, Calif., Nov. 14, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, and Samtec, a leading...
eSilicon to be Acquired by Inphi and Synopsys
November 11, 2019 08:33 ET
|
eSilicon Corporation
SAN JOSE, Calif., Nov. 11, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the signing of a...
eSilicon Announces Availability of 7nm High-Bandwidth Interconnect (HBI+) PHY for Die-to-Die Interconnects
September 22, 2019 00:00 ET
|
eSilicon Corporation
SAN JOSE, Calif., Sept. 22, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today its 7nm...
CORRECTING and REPLACING -- eSilicon Corporation
September 19, 2019 13:38 ET
|
eSilicon Corporation
SAN JOSE, Calif., Sept. 19, 2019 (GLOBE NEWSWIRE) -- In a release issued under the same headline today by eSilicon Corporation, please note that in the headline of the release, it should be...
ECOC 2019: eSilicon to Demonstrate 7nm 58G DSP-Based SerDes Over Seven-Meter and Three-Meter Samtec Cable Assemblies
September 19, 2019 08:00 ET
|
eSilicon Corporation
SAN JOSE, Calif., Sept. 19, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, and Samtec, a leading...
AI Hardware Summit 2019: Booth-to-Booth eSilicon 58G DSP-Based SerDes Demonstration Over a Five-Meter Samtec Copper Cable
September 12, 2019 16:34 ET
|
eSilicon Corporation
SAN JOSE, Calif., Sept. 12, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will partner with Samtec,...
eSilicon to debut AI Accelerator software and a new chiplet model at Hot Chips 2019
August 15, 2019 09:10 ET
|
eSilicon Corporation
New software maps high-level AI workloads to eSilicon’s neuASIC modular AI ASIC IP platform SAN JOSE, Calif., Aug. 15, 2019 (GLOBE NEWSWIRE) -- What eSilicon, an independent provider of...
eSilicon, Samtec and Wild River Technology Offer High-Performance Communications Webinar
June 20, 2019 02:00 ET
|
eSilicon Corporation
SAN JOSE, Calif., June 20, 2019 (GLOBE NEWSWIRE) -- eSilicon, Samtec and Wild River Technology will collaborate to present a webinar that details what is required to deliver high-performance...
eSilicon to Participate in Panel Discussion on Chiplet Design Experience at a Workshop presented by the Open Compute Project (OCP)
June 06, 2019 18:10 ET
|
eSilicon Corporation
SAN JOSE, Calif., June 06, 2019 (GLOBE NEWSWIRE) -- What Chiplet design experience panelA portion of the ODSA workshop will focus on chiplets in three areas: (1) building a proof-of-concept,...
Google and eSilicon at DAC 2019: Doing EDA in the Cloud? Yes, It’s Possible!
May 29, 2019 02:00 ET
|
eSilicon Corporation
SAN JOSE, Calif., May 29, 2019 (GLOBE NEWSWIRE) -- Google and eSilicon will present eSilicon’s journey to ASIC and IP design in the cloud. What EDA in the Cloud? Yes, It’s Possible! We often hear...