Tela Introduces New Lithography-Optimized Standard Cell Libraries for 32/28nm and 22/20nm Processes

LOS GATOS, CA--(Marketwire - Jun 4, 2012) - Tela Innovations, which provides design solutions to enable continued cost-effective scaling of semiconductor manufacturing, today announced the availability of new standard cell libraries optimized for manufacturing processes of 32/28nm and 22/20nm. The foundry-independent libraries leverage Tela's unique proactive approach to the design challenges posed by lithography constraints at 28nm and below.

The Tela approach embraces the inherent lithography constraints and results in designs with simpler, more manufacturable shapes. This is in contrast to an ever-increasing set of highly complex, design rule restrictions that attempt to preserve complex layout structures from previous generations. While the popular belief is that preserving these complex structures is required for area scaling, Tela has demonstrated that this is not the case.

From a designer's perspective Tela's approach to layout is transparent, as the libraries contain a complete set of functions that provide the ability to implement optimized designs based on all of their specific performance, power and area (PPA) requirements. In addition, the Tela libraries go further and introduce cell options for routability tradeoffs providing additional design flexibility.

"These new libraries build on our proven expertise in addressing the unprecedented constraints on design posed by today's most advanced manufacturing processes but also exploit the advantages of the new technologies such as high-K metal gates (HKMG) and local interconnects to the maximum extent possible," said Scott Becker, President and CEO of Tela. "We will continue to combine our knowledge of standard cell design and customer design flows with our many years of innovations to implement highly manufacturable libraries that support the entire gamut of modern SoC design techniques."

Comprehensive libraries for advanced nodes

The 32/28nm libraries are available in architectures optimized for density or speed, and support poly-silicon gate as well as high-K metal gate, gate first and gate last, processes. They come with a complete set of logic and storage elements with multiple circuit variants, including drive strengths and parametric trade-offs, as well as specialized cells to implement arithmetic and register file functions. The libraries support traditional back-end, physical EDA views, including GDSII, schematics and circuit simulation.

The libraries are capable of supporting Tela's gate length biasing technology while maintaining maximum layout pattern uniformity, and also include support for the full range of Vt's available. Gate length biasing techniques provide a significantly better leakage vs. speed trade-off option for designers compared to multi-Vt techniques.

For 22/20nm libraries, the absence of a new generation of lithography like EUV introduces new challenges. Printing 20nm features with 193nm light requires new design approaches encompassing not only Restricted Design Rules (RDR) but double patterning compatible layout as well. The introduction of double patterning for metal layers and local interconnects creates additional complexities for chip designers. Tela's layout in its 22/20nm library ensures the cleanest pattern splitting, resulting in highly manufacturable patterns on the masks. These libraries also incorporate innovative circuit and layout design techniques to maximize the benefit of new process features such as local interconnect, resulting in a superior cell library.

These new libraries are available now from Tela. Due to the more simplified architecture of these libraries they can also be quickly customized to specific customer requirements. For more information about these libraries, please visit our web site at www.tela-inc.com/physical-ip/ or feel free to contact us directly through our web site.

About Tela
Tela Innovations is a privately-held company based in Los Gatos, California that provides solutions addressing the challenge of scaling semiconductor design and manufacturing to advanced process nodes. Tela was founded in 2005 by a team of experts in semiconductor IP, design automation and process technology, and is backed by a number of venture firms and corporate investors, including Intel Capital, Cadence Design Systems, KT Venture Group, LLC, the investment partner of KLA-Tencor Corporation, and Qualcomm Incorporated. For more information on the company visit www.tela-inc.com.

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