eSilicon to exhibit at Hot Chips 2018: A Symposium on High-Performance Chips, Cupertino, California, August 19-21

SAN JOSE, Calif., Aug. 16, 2018 (GLOBE NEWSWIRE) -- eSilicon, an independent provider of FinFET-class ASIC design, market-specific IP platforms and advanced 2.5D packaging solutions, will exhibit at the Hot Chips Conference at the Flint Center in Cupertino, California on August 19-21. Registration for the conference is still open online or on site at the event registration booth.

Update on the neuASIC AI Chip Platform
Artificial intelligence (AI) requires a new and differentiated set of hardware architectures. It is well known that an ASIC will deliver the best power, performance and lowest total cost of ownership, yet, up to now, hardware accelerators for machine learning have been built primarily with GPUs and FPGAs. Algorithms are still changing frequently as they are adapted to the end application and to the latest research in the field, making it problematic to use a static, full-custom ASIC.

eSilicon’s neuASIC™ platform, announced in June 2018, addresses the challenge of evolving algorithms through a portfolio of AI-specific IP and a modular design methodology that allows for easily adaptable ASICs that are extremely efficient.

About eSilicon
eSilicon is an independent provider of complex FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete 2.5D/HBM2 and TCAM platforms for FinFET technology at 16/14/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets.

www.esilicon.com

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eSilicon is a registered trademark, and neuASIC and the eSilicon logo are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.