NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications
10 déc. 2019 10h00 HE
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SmartDV
SAN JOSE, Calif., Dec. 10, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced NSITEXE licensed its...
SmartDV’s TileLink, Verilator VIP on Full Display at RISC-V Summit
03 déc. 2019 10h00 HE
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SmartDV
SAN JOSE, Calif., Dec. 03, 2019 (GLOBE NEWSWIRE) -- WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification and Design Intellectual Property (IP) WHAT: Will highlight new...
SmartDV’s Platform-Independent VIP Portfolio Ensures Seamless Coverage-Driven Verification Flow
21 nov. 2019 11h00 HE
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SmartDV
SAN JOSE, Calif., Nov. 21, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced its broad portfolio of...
SmartDV to Exhibit at SemIsrael Expo, ICCAD China 2019
06 nov. 2019 11h00 HE
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SmartDV
SAN JOSE, Calif., Nov. 06, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies will exhibit at SemIsrael Expo 2019 in Airport City, Israel, November 19 and ICCAD China 2019 November 21-22 in Nanjing,...
SmartDV Heads to DVCon Europe to Showcase VIP Support for Verilator and TileLink, Demonstrate Smart ViPDebug Protocol Debugger
17 oct. 2019 11h00 HE
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SmartDV
SAN JOSE, Calif., Oct. 17, 2019 (GLOBE NEWSWIRE) -- WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation,...
SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator
01 oct. 2019 10h00 HE
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SmartDV
SAN JOSE, Calif., Oct. 01, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the...
SmartDV Announces Availability of Ethernet TSN Design IP
17 sept. 2019 08h00 HE
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SmartDV
SAN JOSE, Calif., Sept. 17, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Design and Verification Intellectual Property (IP), today announced its Design IP for...
SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India
10 sept. 2019 11h00 HE
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SmartDV
SAN JOSE, Calif., Sept. 10, 2019 (GLOBE NEWSWIRE) -- WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation, field...
SmartDV to Exhibit at OpenPower Summit August 19-20
13 août 2019 11h00 HE
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SmartDV
SAN JOSE, Calif., Aug. 13, 2019 (GLOBE NEWSWIRE) -- WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation emulation, field...
SmartDV Adds DisplayPort 2.0 to its Portfolio of Verification IP
16 juil. 2019 11h00 HE
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SmartDV
New VIP for Popular Video Interface Standard Delivered Quickly Via Proprietary SmartDV Compiler, Talented Engineering Group SAN JOSE, Calif., July 16, 2019 (GLOBE NEWSWIRE) -- SmartDV™...