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Accellera Announces IEEE 1800™-2023 Standard Available Through IEEE GET Program
04 mars 2024 12h30 HE | Accellera Systems Initiative
Accellera Announces IEEE 1800™-2023 Standard Available Through IEEE GET Program
Meridian RXV
Real Intent Provides Comprehensive Reset Analysis with Meridian RXV
29 oct. 2018 08h00 HE | Real Intent
New Tool Offers Reset Audit, Reset Optimization and RTL X-Optimism Analysis SUNNYVALE, Calif., Oct. 29, 2018 (GLOBE NEWSWIRE) -- Real Intent, Inc., a leading provider of SoC and FPGA sign-off...
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Open-Silicon Appoints New VP of Engineering
18 sept. 2018 08h00 HE | Open-Silicon
MILPITAS, Calif., Sept. 18, 2018 (GLOBE NEWSWIRE) -- Amid rapid custom silicon growth and innovation, Open-Silicon today announced the appointment of semiconductor industry veteran Anand Bariya as...
Real Intent to Exhib
Real Intent to Exhibit New Products at the 55th DAC in San Francisco
19 juin 2018 08h00 HE | Real Intent, Inc.
SUNNYVALE, Calif., June 19, 2018 (GLOBE NEWSWIRE) -- What:Real Intent will showcase its new Verix family of products including the just announced PhyCDC product for gate-level CDC sign-off and...
Verix
Real Intent Launches Verix PhyCDC – the Next Innovation in SoC Design Sign-off
18 juin 2018 08h00 HE | Real Intent, Inc.
SUNNYVALE, Calif., June 18, 2018 (GLOBE NEWSWIRE) -- Real Intent, Inc., a leading provider of SoC and FPGA sign-off verification solutions, today announced Verix PhyCDC – a new tool to debug clock...
Real Intent's New Ve
Real Intent's New Verix SimFix Software Delivers First Intent-Driven Remedy for Verification Pessimism
30 mai 2018 08h00 HE | Real Intent, Inc.
SUNNYVALE, Calif., May 30, 2018 (GLOBE NEWSWIRE) -- Real Intent, a leading provider of SoC and FPGA sign-off verification solutions, today launched Verix SimFix, the first intent-driven verification...
Sidense SHF Embedded Memory Macros Target High-Performance and Low-Power Applications in TSMC 28nm Processes
29 mai 2014 09h00 HE | Sidense
OTTAWA, ON--(Marketwired - May 29, 2014) - Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that the Company's 1T-OTP macros for TSMC's 28nm HPL, HPM and HPC...
eSilicon Engineers' Comprehensive Book on Low-Power Design for ASICs Is Now Available
05 févr. 2013 08h00 HE | eSilicon
SUNNYVALE, CA--(Marketwire - Feb 5, 2013) - eSilicon Corporation, the largest independent semiconductor design and manufacturing services provider, today announced that An ASIC Low-Power Primer is...