SAN JOSE, Calif., May 17, 2010 (GLOBE NEWSWIRE) -- Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, today announced Titan™ Analog Layout Accelerator (ALX) and Titan Analog Virtual Prototyper (AVP), new tools that accelerate the creation and optimization of new analog design layouts, and automate the reuse of existing analog layouts in new processes and technologies.
Augmenting the comprehensive Titan Mixed-Signal Design Platform, Titan ALX and Titan AVP are part of a unique set of plug-and-play analog design solutions known as the Titan accelerators. Based on breakthrough analog design technology, and featuring dramatic new capabilities and compatibility with existing analog tool flows, the Titan accelerators deliver an order-of-magnitude productivity improvement for analog/mixed-signal layout designers.
Titan ALX automatically migrates an existing analog layout to a new target technology without any DRC violations while preserving analog design intent. Titan AVP creates fast and accurate device-level prototypes and captures layout-dependent proximity effects early in the circuit design phase. Early visibility into parasitic R and C, as well as proximity effects such as shallow trench isolation (STI) stress, well proximity effect (WPE), oxide definition to oxide definition (OD-OD) spacing and poly to poly spacing accelerate schematic-layout convergence. Titan AVP also includes a detailed device placement engine that produces a high-quality, DRC-clean layout. The capabilities delivered in these two new Titan accelerators dramatically reduce analog layout creation time.
"The number of chips that use both digital and analog components is increasing. As a result, there's growing demand for a methodology for creating reusable and portable analog designs," said Anirudh Devgan, general manager of Magma's Custom Design Business Unit. "With the addition of Titan ALX and Titan AVP to the Titan family, Magma provides high-productivity analog design layout tools that allow chipmakers to build differentiated analog products faster, accelerate the adoption of newer process technologies – and ultimately achieve a higher return on design investment."
Titan: Automating and Accelerating Analog Design and Reuse
Titan ALX and Titan AVP are the latest additions to the Titan family of accelerators. These targeted solutions enable analog IP reuse and rapid design exploration, and automate layout creation and process porting. Titan accelerators provide new options to analog designers facing increasingly complex challenges in custom circuit design. Each product can be used to augment an existing design flow, or combined with the Titan Mixed-Signal Design Platform to create a comprehensive mixed-signal design solution.
The Titan platform includes the following:
- Titan ADX Analog Design Accelerator: Model-based analog design and optimization solution that enables reuse of analog blocks. It is available with pre-built FlexCell libraries of analog building blocks.
- Titan AVP Analog Virtual Prototyper: Layout-aware schematic design tool that enables simultaneous electrical and physical co-design.
- Titan SBR Shape-Based Router: Automates difficult routing tasks including analog routing, clock/DDR routing and chip-level assembly routing, providing a 10x improvement in productivity.
- Titan ALX Analog Layout Accelerator: Automatically migrates analog cell layouts to new processes while preserving design intent.
- Titan Mixed-Signal Design Platform: The industry's first true mixed-signal design platform, it integrates implementation and verification while delivering first-time-correct, predictable mixed-signal designs. The Titan Mixed-Signal Design Platform includes a schematic editor, a complete analog simulation environment and a schematic-driven layout capability that works with the layout editor. The Titan platform is tightly integrated with the Talus® digital implementation tools and provides a chip finishing flow to deliver a comprehensive mixed-signal design solution.
Availability
Titan ALX and Titan AVP will be in production release in June 2010.
About Magma
Magma's electronic design automation (EDA) software provides the "Fastest Path to Silicon"™ and enables the world's top chip companies to create high-performance integrated circuits (ICs) for cellular telephones, electronic games, WiFi, MP3 players, digital video, networking and other electronic applications. Magma products are used in IC implementation, analog/mixed-signal design, analysis, physical verification, circuit simulation and characterization. The company maintains headquarters in San Jose, Calif., and offices throughout North America, Europe, Japan, Asia and India. Magma's stock trades on Nasdaq under the ticker symbol LAVA. Follow Magma on Twitter at www.Twitter.com/MagmaEDA and on Facebook at www.Facebook.com/Magma. Visit Magma Design Automation on the Web at www.magma-da.com.
Magma and Talus are registered trademarks and "Fastest Path to Silicon" and Titan are trademarks of Magma Design Automation Inc. All other product and company names are trademarks and registered trademarks of their respective companies.
Forward-looking Statements:
Except for the historical information contained herein, the matters set forth in this press release, including statements that Titan provides a10x improvement in designer productivity and other statements about the features and benefits of Magma software are forward-looking statements within the meaning of the "safe harbor" provisions of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially, including but not limited to the ability of Magma products and services to produce the desired results and the company's ability to keep pace with rapidly changing technology. Further discussion of these and other potential risk factors may be found in Magma's public filings with the Securities and Exchange Commission (www.sec.gov). The company undertakes no additional obligation to update these forward-looking statements.