SUNNYVALE, CA--(Marketwire - May 24, 2012) -
Create Superior Products with Selective Memory Customization
ChipEstimate IP Talks: Booth #1202
Patrick Soheili, eSilicon's VP and GM, IP Solutions Group, will be presenting Create Superior Products with Selective Memory Customization at ChipEstimate IP Talks. Learn how custom IP can optimize your chip's power, performance or area.
- Monday, June 4,10:00 AM
- Tuesday, June 5, 2:30 PM
- Wednesday, June 6, 11:00 AM
Synopsys Next-Generation Hierarchical Timing Technology - HyperScale
Synopsys PrimeTime SIG at DAC 2012
Prasad Subramaniam, eSilicon's VP of design technology, will be hosting a table at the Synopsys Primetime SIG event.
When:
Monday, June 4, 6:00 - 8:30 PM
Where:
Francisco Marriott Marquis, Golden Gate Ballroom A 55 Fourth Street
Dinner and beverages are complimentary
Divide and Conquer - Intelligent Partitioning
Magma/Synopsys Booth #310
This panel will discuss what's needed from synthesis, verification and physical design tools to make partitioning work for today's designs, budgets, resources and delivery schedules.
When:
Wednesday, June 6, 1:30 - 2:15 PM
Moderator:
Paul McLellan - SemiWiki
Speakers:
Hao Nham - eSilicon Corporation
Jonathan DeMent - IBM Systems and Technology Group
Santosh Santosh - NVIDIA Corporation
Satiating the Hunger for Memory Bandwidth in Networking Applications
TSMC OIP: TSMC DAC Theater
Patrick Soheili, eSilicon's VP and GM, IP Solutions Group, will present how specialized memory products, such as content-addressable memory (CAM) and multi-port register files can be used in networking applications.
- Tuesday, June 5, 4:15 - 4:25 PM
- Wednesday, June 6, 10:15 - 10:25 AM
eSilicon is a registered trademark, and the eSilicon logo and Enabling Your Silicon Success are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.
Contact Information:
For more information or to schedule a meeting with eSilicon at DAC, contact:
Susan Cain
Cain Communications
503-538-2747