eSilicon at DAC 2015: New Online Tools, Lower Power/Smaller Die, IoT and IP Parties

SAN JOSE, CA--(Marketwired - Jun 2, 2015) - eSilicon, a leading semiconductor design and manufacturing solutions provider, will participate in several venues at the 2015 Design Automation Conference (DAC) at Moscone Center in San Francisco, Calif., June 8-10, 2015.

What:
ARM Connected Community Pavilion: Designing and manufacturing for complex ARM-based designs
Who: 
Mike Gianfagna, eSilicon VP of marketing, to discuss how eSilicon solutions enable complex ARM-based designs as well as the new online ASIC design products and services
When:
Monday, June 8, 5:45 PM
Wednesday, June 10, 1:15 PM
Where: 
ARM Pavilion Booth 2414

What:
ChipEstimate IP Talks: Gambling is fun, but not with your chip
Who:
Lisa Minwell, eSilicon's senior director of IP marketing, will discuss ways to win in your market with lower power and a smaller die
When:
Monday, June 8, 11:00 AM
Tuesday, June 9, 5:30 PM
Wednesday, June 10, 4:00 PM
Where:
ChipEstimate Booth 2433

What:
Panel: Meeting exploding demand throughout the ecosystem
Who:
Moderator: Michael Buehler-Garcia, senior director of marketing for Calibre Design Solutions, Mentor Graphics
Panelists:
Kelvin Low, senior director of foundry marketing, Samsung
Prasad Subramaniam, VP of design technology and R&D, eSilicon
Walter Ng, VP, business development, UMC USA
When:
Monday, June 8, 4:00 PM
Where:
Mentor Graphics Booth 1432

What:
How low can power go? Ultra-low-power IP for IoT wearables
Who:
Lisa Minwell, eSilicon's senior director of IP marketing, will present how to optimize your low-power ASIC for internet of things applications
When: 
Monday, June 8, 3:15 PM
Tuesday, June 9, 2:45 PM
Wednesday, June 10, 11:45 AM
Where:
TSMC Booth 1933

What:
Moving the semiconductor industry to the Internet
Who:
Geoff Porter, eSilicon's director of client marketing
When: 
Wednesday, June 10, 3:10 PM
Where:
SMIC Booth 2803

What:
ASIC design in the Internet age
Who:
Javier DeLaCruz, eSilicon's senior director of product strategy
When: 
Tuesday, June 9, 3:30 PM
Where:
Samsung Booth 933

What:
Synopsys custom design luncheon
Who:
Deepak Sabharwal, eSilicon's vice president of engineering for IP
When: 
Tuesday, June 9, 11:30 AM
Where:
Park Central Hotel (formerly Westin)
Metropolitan Ballroom III
50 Third Street
San Francisco, CA 94103

What:
Love IP Party
Who:
Proceeds will benefit the San Jose State University Guardian Scholars Program
When:
Monday, June 8, 7:00 PM to 11:30 PM
Where:
Jillian's SF at the Metreon, (15-minute walk from Moscone Center) Performances by the Sonics and Groovy Love Band plus an open bar with 17 microbrews on tap and specialty cocktails

What:
Stars of IP Party
When:
Tuesday, June 9, 9:00 PM to 1:00 AM
Where:
Novela
662 Mission Street (10-minute walk from Moscone Center)
Hosted bar, heavy hors d'oeuvres, entertainment and surprises

About eSilicon
eSilicon guides customers through a fast, accurate, transparent, low-risk ASIC journey, from concept to volume production. Explore your options online with eSilicon STAR tools, engage with eSilicon experts, and take advantage of eSilicon semiconductor design, custom IP and IC manufacturing solutions through a flexible engagement model. eSilicon serves a wide variety of markets including the communications, computer, consumer, industrial products and medical segments. Get the data, decision-making power and technology you need for first-time-right results. www.esilicon.com

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