SUNNYVALE, Calif., June 19, 2018 (GLOBE NEWSWIRE) --
What:
Real Intent will showcase its new Verix family of products including the just announced PhyCDC product for gate-level CDC sign-off and SimFix for eliminating X-pessimism, at the 55th Design Automation Conference (DAC) in San Francisco, CA, June 25-June 27. The two new products join Verix CDC, the company’s multi-mode CDC solution.
DAC attendees can register for a suite appointment at www.realintent.com/DAC/ where the company has just completed a full re-design of its website, making it easier to navigate and quickly find the resources to learn more about the company and its products. Attendees may also register in person at the Real Intent booth.
Exhibit Information:
Booth 1431
Moscone Convention Center
Exhibit hours: Monday, June 25 - Wednesday, June 27 from 10:00am – 6:00pm
Products on display include:
- Verix PhyCDC is the company’s new tool for debugging clock domain crossing violations at the gate level netlist of digital designs. It targets the post-synthesis stage of SoC design at the gate level, and leverages the results from RTL CDC to identify incremental CDC paths and constraints to optimize the CDC analysis while providing maximum coverage. For more information on Verix PhyCDC, a whitepaper and data sheet are available.
- Verix SimFix automatically eliminates X-pessimism, the major obstacle to successful GLS and boosts productivity for SoC design teams. This new product also extends Real Intent's product leadership in delivering the industry's fastest performance, highest capacity, and most productive verification solutions in the market. For more information on Verix SimFix, a data sheet and DeepChip coverage are available.
- Verix CDC is a true multi-mode clock-domain crossing (CDC) sign-off solution for RTL designs. Utilizing Static Intent Verification technology, it provides one-step analysis and debug of all operating modes in an IC, and boosts productivity for SoC and FPGA design teams. It also maintains Real Intent's product leadership in delivering what the company believes is the industry's fastest-performance, highest-capacity and most precise CDC solution in the market. For more on Verix CDC, a whitepaper and data sheet are available.
- The Meridian products are for advanced static clock and reset sign-off verification not possible with existing tools.
Real Intent’s Hierarchical capability, introduced for Meridian CDC, has now been extended to Meridian RDC. It delivers cutting edge sign-off for billion-gate SoCs using the industry’s first Transparent Hierarchical Model (THM). The THM-based signoff flow provides an order of magnitude improvement in performance, capacity with giga-gate sign-off, and noise when applied to large SoC designs.
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- Meridian CDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. Meridian CDC is the only solution that enables all aspects of big data CDC sign-off for SoC designs.
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- Meridian RDC (Reset Domain Crossing) performs comprehensive static analysis to ensure that signals crossing reset domains function reliably. Among other things, Meridian RDC identifies metastability problems arising from software resets. Meridian RDC is the only solution with giga-gate capacity that enables comprehensive lowest-noise reset domain crossing sign-off.
- Ascent Lint is the industry’s fastest RTL linter and rule checker for full-chip SoC analysis. Designed from the bottom-up to deliver the highest performance, capacity and low-noise reporting, it is the best-in-class HDL linter available today with a comprehensive set of syntax and semantic checks.
- iDebug provides an intuitive debug user experience that is universal across all Real Intent tools. It includes an integrated visualization capability, iVision, that provides design source browser, schematic and waveform visualization. It also includes a new Intent Wizard platform that provides unprecedented gains in static sign-off productivity. The Intent Wizard platform uses comprehensive data generated by Real Intent’s static sign-off application engine and combines that with the Root Cause Analysis technology within iDebug to cut the debug time in half.
Website Redesign
The newly designed www.realintent.com website provides a sleek new look that makes it much easier for visitors to learn about the company’s verification solutions and navigate through resources such as videos, whitepapers, data sheets and company background material.
About Real Intent
Real Intent is the industry leader in static sign-off of digital designs. Companies worldwide rely on Real Intent's EDA software to accelerate early functional verification and sign-off at RTL as well as gate-level. Its intent-driven static technology powers solutions for clock and reset domain crossing analysis (CDC, RDC), and cleaned RTL code and X-pessimism correction, to ensure design success for SoCs and FPGAs. Real Intent products lead the market in performance, capacity and accuracy, and provide a faster time to tape out. Please visit www.realintent.com for more information.
Verix, Ascent, and Meridian are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
Press contact:
Barbara Benjamin for Real Intent
HighPointe Communications
503.209.2323
barbara@hipcom.com