LOUISVILLE, Colo., Feb. 24, 2020 (GLOBE NEWSWIRE) -- The 32nd annual Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative, begins next week with an information-packed, comprehensive four-day technical program. DVCon U.S. will be held March 2-5 at the DoubleTree Hotel in San Jose, California.
Attendees can look forward to a wide variety of topics among the 40 technical papers, four tutorials, 20 posters, 10 short workshops and two panels. The keynote address will focus on artificial intelligence for design automation.
Accellera Day opens the conference on Monday with a full morning tutorial, “Portable Stimulus: What’s Coming in 1.1 and What it Means for You” presented by members of the Accellera Portable stimulus Working Group. An Accellera-sponsored luncheon will follow with updates on Accellera activities, the presentation of the 2020 Technical Excellence Award, an update from the new Functional Safety Working Group Chair, and a panel focused on Portable Stimulus. Monday afternoon will have six short workshops to choose from, followed by the opening of the exhibition and reception.
Tuesday begins with paper sessions on Formal Verification I, Portable Stimulus and Automating Verification Solutions, followed by the poster session. The keynote address, “Artificial Intelligence for Design Automation,” will be presented by Dr. Anirudh Devgan, president of Cadence Design Systems. Tuesday afternoon there will be sessions on UVM Strategies, Verification Potpourri and Power-Aware Design and Verification.
Wednesday will feature two panels: “New Chip Designs Create a Tidal Wave of Change” and “Predicting the Verification Flow of the Future.” Paper sessions include: Hybrid Verification, Verification Strategies, Formal Verification II, Verification Processes and Methodologies, SystemVerilog Solutions, and Reset Domain Challenges.
Thursday will have three sponsored morning tutorials followed by four afternoon short workshops. For a complete list of the topics and presenters on Thursday, visit the agenda.
In addition to the Accellera-sponsored luncheon on Monday, Cadence will host the luncheon on Tuesday, “Towards Intelligent System Design with AI Enabled EDA.” Wednesday’s luncheon will be hosted by Synopsys, “Industry Leaders Verify with Synopsys,” and the luncheon on Thursday, “Optimizing Time to Bug, Don’t Panic!!” will be hosted by Mentor, A Siemens Business.
The DVCon Expo will be open Monday evening from 5:00-7:00pm and Tuesday and Wednesday from 2:30-6:00pm. There will be a reception each evening during the Expo.
For the complete DVCon U.S. 2020 schedule, including more detailed information on each session, visit www.dvcon.org. To register, visit here.
About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.
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| Nannette Jordan MP Associates, Inc. 303-530-4562 nannette@mpassociates.com | Barbara Benjamin HighPointe Communications 503-209-2323 barbara@hipcom.com |