San Jose, CA, Nov. 06, 2020 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding Premier member of RISC-V International will make six presentations at the virtual RISC-V Summit from December 8 to 10, 2020.
Andes CTO and Executive VP, Charlie Hong-Men Su, will give an overview and update on "Andes RISC-V Processor IP Solutions." Andes Senior Director of Architecture Div., Chuan-Hua Chang, will present "AndesClarity: a Performance & Bottleneck Analyzer for RISC-V Vector Processors." Paul Ku, Deputy Technical Director of Architecture Div., will introduce "Building a Secure Platform with the Enhanced IOPMP."
The SoC industry has seen fast-growing and diversified demands for a wide range of RISC-V based products: from tiny low-power MCUs for consumer devices, to chips powering enterprise-grade products and datacenter servers; from one power-efficient core to a thousand GHz+ cores working cohesively. Charlie Su will explain the rich portfolio of AndesCore™ RISC-V processor IPs already populating these SoCs: compact single-issue cacheless cores to feature-rich Linux-capable superscalar cores, cache-coherence multicores, and cores capable of processing floating-point and DSP data to those crunching a large volume of vector data. He will also update RISC-V IPs newly added to Andes processor portfolio, the associated software support and their performance data.
Additionally, Deputy Software Manager, Shao-Chung Wang, will present "Extending Multicore Programming Framework for Vector Extension." Ding-Kai Huang, VLSI Manager, will discuss "Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV," co-authored with Tao Liu from Google. Andes Principal Architect, Thang Tran, will hold a 3-hour master class entitled "RISC-V Vector Extension Demystified."
For more information, please visit the RISC-V Summit website.
●Charlie Su's presentation "Andes RISC-V Processor IP Solutions" will occur on December 8 from 3:00 to 3:20 pm.
● Shao-Chung Wang will introduce "Extending Multicore Programming Framework for Vector Extension" on December 8 from 3:20 to 3:30 pm.
● Ding-Kai Huang will present "Enhancing Verification Coverage for RISC-V Vector Extension Using RISCV-DV" on December 9 from 12:00 to 12:20 pm.
● Paul Ku's presentation "Building a Secure Platform with the Enhanced IOPMP" will take place on December 9 from 2:30 to 2:50 pm.
● Chuan-Hua Chang will present "AndesClarity: a Performance & Bottleneck Analyzer for RISC-V Vector Processors" on December 9 from 3:30 to 3:50.
●Thang Tran's tutorial "RISC-V Vector Extension Demystified" will take place on December 10 from 2:00 to 5:00 pm.
About Andes Technology
Fifteen years in business and a founding Premier member of RISC-V International, Andes Technology is a leading supplier of high-performance, low-power 32/64-bit embedded processor IP solutions and a major player in pushing RISC-V into the mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as its base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, dual-issue, and/or multi-core capabilities. Visit Andes at https://www.andestech.com.