SmartDV Adds Support for MIPI I3C 1.1 Across Entire IP Portfolio
February 12, 2020 10:30 ET
|
SmartDV
SAN JOSE, Calif., Feb. 12, 2020 (GLOBE NEWSWIRE) -- SmartDV™ Technologies today announced its entire IP portfolio supports the new MIPI I3C® v1.1 utility and control bus specification designed to...
SmartDV Achieves Record Revenue in 2019
February 04, 2020 11:00 ET
|
SmartDV
SAN JOSE, Calif., Feb. 04, 2020 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Design and Verification Intellectual Property (IP), today announced record revenue and...
NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications
December 10, 2019 10:00 ET
|
SmartDV
SAN JOSE, Calif., Dec. 10, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced NSITEXE licensed its...
SmartDV’s TileLink, Verilator VIP on Full Display at RISC-V Summit
December 03, 2019 10:00 ET
|
SmartDV
SAN JOSE, Calif., Dec. 03, 2019 (GLOBE NEWSWIRE) -- WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification and Design Intellectual Property (IP) WHAT: Will highlight new...
SmartDV’s Platform-Independent VIP Portfolio Ensures Seamless Coverage-Driven Verification Flow
November 21, 2019 11:00 ET
|
SmartDV
SAN JOSE, Calif., Nov. 21, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP), today announced its broad portfolio of...
SmartDV to Exhibit at SemIsrael Expo, ICCAD China 2019
November 06, 2019 11:00 ET
|
SmartDV
SAN JOSE, Calif., Nov. 06, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies will exhibit at SemIsrael Expo 2019 in Airport City, Israel, November 19 and ICCAD China 2019 November 21-22 in Nanjing,...
SmartDV Heads to DVCon Europe to Showcase VIP Support for Verilator and TileLink, Demonstrate Smart ViPDebug Protocol Debugger
October 17, 2019 11:00 ET
|
SmartDV
SAN JOSE, Calif., Oct. 17, 2019 (GLOBE NEWSWIRE) -- WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation,...
SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator
October 01, 2019 10:00 ET
|
SmartDV
SAN JOSE, Calif., Oct. 01, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the...
SmartDV Announces Availability of Ethernet TSN Design IP
September 17, 2019 08:00 ET
|
SmartDV
SAN JOSE, Calif., Sept. 17, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Design and Verification Intellectual Property (IP), today announced its Design IP for...
SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India
September 10, 2019 11:00 ET
|
SmartDV
SAN JOSE, Calif., Sept. 10, 2019 (GLOBE NEWSWIRE) -- WHO: SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (VIP) supporting simulation, emulation, field...